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preliminary 16-mbit (1m x 16) pseudo static ram CYU01M16SCG mobl3? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-09739 rev. ** revised august 7, 2006 features ? wide voltage range: 2.2v?3.6v ? access time: 70 ns ? ultra-low active power ? typical active current: 3 ma @ f = 1 mhz ? typical active current: 18 ma @ f = f max ? ultra low standby power ? automatic power-down when deselected ? cmos for optimum speed/power ? offered in a 48-ball bga package ? operating temperature: ?40c to +85c functional description [1] the CYU01M16SCG is a high -performance cmos pseudo static ram organized as 1m words by 16 bits that supports an asynchronous memory interfac e. this device features advanced circuit design to provide ultra-low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device can be put into standby mode when deselected (ce 1 high or ce 2 low or both bhe and ble are high). the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when: deselected (ce 1 high or ce 2 low), outputs are disabled (oe high), both byte high enable and byte low enable are disabled (bhe , ble high), or during a write operation (ce 1 low and ce 2 high and we low). to write to the device, take chip enable (ce 1 low and ce 2 high) and write enable (we ) input low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 19 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 19 ). to read from the device, take chip enables (ce 1 low and ce 2 high) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . refer to the truth table for a complete description of read and write modes. note: 1. for best-practice recommendations, please refer to the cypress application note ?system design guidelines? on http://www.cypr ess.com. 1m x 16 ram array i/o 0 ?i/o 7 column decoder sense amps data in drivers oe i/o 8 ?i/o 15 we ble bhe row decoder power -down circuit bhe ble a 8 a 7 a 6 a 5 a 4 a 3 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 a 17 a 19 a 18 ce 2 ce 1 ce 2 ce 1 a 2 a 1 a 0 logic block diagram [+] feedback [+] feedback
preliminary CYU01M16SCG mobl3? document #: 001-09739 rev. ** page 2 of 11 power-up characteristics the initialization sequence is shown in the figure below. chip select should be ce 1 high or ce 2 low for at least 200 s after v cc has reached a stable value. no access must be attempted during this period of 200 s. pin configuration [2, 3] 48-ball vfbga we a 11 a 10 a 6 a 0 a 3 ce 1 i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe v ss a 7 i/o 0 bhe ce 2 a 17 a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 3 2 6 5 4 1 d e b a c f g h top view a 16 nc v cc a 18 nc a 19 product portfolio [4] product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( a) f = 1mhz f = f max CYU01M16SCG min. typ. [4] max. typ. [4] max. typ. [4] max. typ. [4] max. 2.2 3.0 3.6 70 3 5 18 25 55 70 parameter descripti on min. typ. max. unit tpu chip enable low after stable v cc 200 s notes: 2. ball h6 and e3 can be used to upgrade to a 32-mbit and a 64-mbit density, respectively. 3. nc ?no connect? - not connected internally to the die. 4. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc (typ) and t a = 25c. tested initially and after design changes that may affect the parameters. tpu ce v cc first access stable power [+] feedback [+] feedback
preliminary CYU01M16SCG mobl3? document #: 001-09739 rev. ** page 3 of 11 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage to ground potential ..............................?0.3v to v ccmax + 0.3v dc voltage applied to outputs in high z state [5, 6, 7] ........................?0.3v to v ccmax + 0.3v dc input voltage [5, 6, 7] .................... ?0.3v to v ccmax + 0.3v output current into outputs (low)............................. 20 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current .................................................... > 200 ma device range operating temperature (t a )v cc CYU01M16SCG industrial ?40c to +85c 2.2v to 3.6v dc electrical characteristics (over the operating range) [5, 6, 7] parameter description test conditions CYU01M16SCG-70 ns unit min. typ. [4] max. v cc supply voltage 2.2 3.0 3.6 v v oh output high voltage i oh = ?0.1 ma v cc = 2.2v to 3.6v v cc ? 0.2 v v ol output low voltage i ol = 0.1 ma v cc = 2.2v to 3.6v 0.2 v v ih input high voltage v cc = 2.2v to 3.6v 0.8 * v cc v cc + 0.3v v v il input low voltage v cc = 2.2v to 3.6v ?0.3 0.2 * v cc v i ix input leakage current gnd < v in < v cc ?1 +1 a i oz output leakage current gnd < v out < v cc ?1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = v ccmax i out = 0 ma cmos levels 18 25 ma f = 1mhz 3 5 ma i sb1 automatic ce power-down current?cmos inputs ce 1 > v cc ? 0.2v, ce 2 < 0.2v, v in > v cc ? 0.2v, v in < 0.2v, f = f max (address and data only), f = 0 (oe , we , bhe and ble ), v cc = 3.60v 55 70 a i sb2 automatic ce power-down current?cmos inputs ce 1 > v cc ? 0.2v, ce 2 < 0.2v, v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc =v ccmax 55 70 a capacitance [8] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ) 8pf c out output capacitance 8 pf thermal resistance [8] parameter description test conditions vfbga unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedence, per eia/jesd51 56 c/w jc thermal resistance (j unction to case) 11 c/w notes: 5. v il(min) = ?0.5v for pulse durations less than 20 ns. 6. v ih(max) = v cc + 0.5v for pulse durations less than 20 ns. 7. overshoot and undershoot spec ifications are characterized and are not 100% tested. 8. tested initially and after any design or process changes that may affect these parameters. [+] feedback [+] feedback
preliminary CYU01M16SCG mobl3? document #: 001-09739 rev. ** page 4 of 11 ac test loads and waveforms v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v th equivalent to: thevenin equivalent all input pulses r th r1 parameters 3.0v (v cc )unit r1 26000 ? r2 26000 ? r th 13000 ? v th 1.50 v switching characteristics over the operating range [9, 10, 11, 14, 15] parameter description 70 ns unit min. max. read cycle t rc [13] read cycle time 70 40000 ns t cd chip deselect time ce 1 = high or ce 2 =low, ble /bhe high pulse time 15 ns t aa address to data valid 70 ns t oha data hold from address change 5 ns t ace ce low to data valid 70 ns t doe oe low to data valid 35 ns t lzoe oe low to low z [10, 11, 12] 5ns t hzoe oe high to high z [10, 11, 12] 25 ns t lzce ce low to low z [10, 11, 12] 10 ns t hzce ce high to high z [10, 11, 12] 25 ns t dbe ble /bhe low to data valid 70 ns t lzbe ble /bhe low to low z [10, 11, 12] 5ns t hzbe ble /bhe high to high z [10, 11, 12] 25 ns notes: 9. test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/v, timing reference levels of v cc(typ.) /2, input pulse levels of 0v to v cc , and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? section. 10. at any given temperature and voltage conditions t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. all low-z parameters will be meas ured with a load capacitance of 30 pf (3v). 11. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high-impedance state. 12. high-z and low-z parameters are characterized and are not 100% tested. 13. if invalid address signals shorter than min.trc are continuously repeated for 40 s, the device needs a normal read timing (t rc ) or needs to enter standby state at least once in every 40 s. 14. in order to achieve 70-ns performance, the read access must be chip enable (ce 1 or ce 2 ) controlled. that is, the addresses must be stable prior to chip enable going active. [+] feedback [+] feedback
preliminary CYU01M16SCG mobl3? document #: 001-09739 rev. ** page 5 of 11 write cycle [15] t wc write cycle time 70 40000 ns t sce ce low to write end 60 ns t aw address set-up to write end 60 ns t cd chip deselect time ce 1 = high or ce 2 =low, ble /bhe high pulse time 15 ns t ha address hold from write end 0 ns t sa address set-up to write start 0 ns t pwe we pulse width 50 ns t bw ble /bhe low to write end 60 ns t sd data set-up to write end 25 ns t hd data hold from write end 0 ns t hzwe we low to high-z [10, 11, 12] 25 ns t lzwe we high to low-z [10, 11, 12] 10 ns note: 15. the internal write time of the memory is defined by the overlap of we , ce 1 = v il or ce 2 = v ih , bhe and/or ble = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going in active. the data input set-up and hold timing should be referen ced to the edge of the signal that terminates the write. switching characteristics over the operating range [9, 10, 11, 14, 15] (continued) parameter description 70 ns unit min. max. [+] feedback [+] feedback
preliminary CYU01M16SCG mobl3? document #: 001-09739 rev. ** page 6 of 11 switching waveforms read cycle 1 (address transition controlled) [17, 18] read cycle 2 (oe controlled) [16, 18, 19] notes: 16. whenever ce 1 = high or ce 2 = low, bhe /ble are taken inactive, they must remain inactive for a minimum of 5 ns. 17. device is continuously selected. oe = ce 1 = v il and ce 2 = v ih . 18. we is high for read cycle. 19. ce is the logical and of ce 1 and ce 2 . address data out previous data valid data valid t rc t aa t oha 50% 50% data valid t rc t ace t doe t lzoe t lzce high impedance t hzoe high oe ce 1 i cc i sb impedanc e address v cc supply current t hzbe bhe / ble t lzbe t hzce data out t dbe t cd ce 2 [+] feedback [+] feedback
preliminary CYU01M16SCG mobl3? document #: 001-09739 rev. ** page 7 of 11 write cycle 1 (we controlled) [15, 12, 16, 19, 20, 21] notes: 20. data i/o is high-impedance if oe > v ih . 21. during the don?t care period in the data i/o waveform, the i/os are in output state and input signals should not be applied. switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe valid data ce 1 address we data i/o oe bhe / ble t bw don?t care t cd ce 2 [+] feedback [+] feedback
preliminary CYU01M16SCG mobl3? document #: 001-09739 rev. ** page 8 of 11 write cycle 2 (ce 1 or ce 2 controlled) [15, 12, 16, 20, 21] write cycle 3 (we controlled, oe low) [16, 21] switching waveforms (continued) t hd t sd t pwe t ha t aw t sce t wc t hzoe valid data ce 1 address ce 2 we data i/o oe don?t care bhe /ble t bw t sa valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce 1 address ce 2 we data i/o t bw bhe / ble don?t care [+] feedback [+] feedback
preliminary CYU01M16SCG mobl3? document #: 001-09739 rev. ** page 9 of 11 write cycle 4 (bhe /ble controlled, oe low) [15, 16, 20, 21] switching waveforms (continued) data i/o address t hd t sd t sa t ha t aw t wc ce 1 we valid data t bw bhe /ble t sce ce 2 t pwe don?t care truth table [22] ce 1 ce 2 we oe bhe ble inputs/outputs mode power hxxxxxhigh z deselect/power-down standby (i sb ) x l x x x x high z deselect/power-down standby (i sb ) x x x x h h high z deselect/power-down standby (i sb ) l h h l l l data out (i/o 0 ?i/o 15 ) read active (i cc ) lhhlhldata out (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high z read active (i cc ) l h h l l h data out (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z read active (i cc ) l h h h l l high z output disabled active (i cc ) lhhhhlhigh z output disabled active (i cc ) l h h h l h high z output disabled active (i cc ) l h l x l l data in (i/o 0 ?i/o 15 ) write (upper byte and lower byte) active (i cc ) l h l x h l data in (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high z write (lower byte only) active (i cc ) l h l x l h data in (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z write (upper byte only) active (i cc ) note: 22. h = logic high, l = logic low, x = don?t care. [+] feedback [+] feedback
preliminary CYU01M16SCG mobl3? document #: 001-09739 rev. ** page 10 of 11 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. mobl is a registered trademark and mob l3 and more battery life are trademarks of cypress semiconductor corporation. all product and company names mention ed in this document may be the trademarks of their respective holders. ordering information speed (ns) ordering code package diagram package type operating range 70 CYU01M16SCG-70bvxi 51-85150 48-ball fine pitch vbga (6 mm 8 mm 1 mm) (pb-free) industrial package diagram a 1 a1 corner 0.75 0.75 ?0.300.05(48x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.00 max c seating plane 0.55 max. 0.25 c 0.10 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 46 5 23 1 d h f g e c b a 6.000.10 8.000.10 a 8.000.10 6.000.10 b 1.875 2.625 0.26 max. 48-ball vfbga (6 x 8 x 1 mm) (51-85150) 51-85150-*d [+] feedback [+] feedback
preliminary CYU01M16SCG mobl3? document #: 001-09739 rev. ** page 11 of 11 document history page document title: CYU01M16SCG mobl3? 16-mbit (1m x 16) pseudo static ram document number: 001-09739 rev. ecn no. issue date orig. of change description of change ** 497844 see ecn nxr new data sheet [+] feedback [+] feedback

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